This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-181877, filed Jun. 28, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a nonvolatile semiconductor memory capable of storing data of a plurality of bits in one cell transistor and, more particularly, to an improvement in the data holding characteristics of the cell transistor.
As a general nonvolatile semiconductor memory, an electrically erasable programmable EEPROM, particularly, a flash memory is well known. The flash memories can be categorized into a NAND type and a NOR type memories. The conventional problems will be explained by exemplifying a NAND flash memory.
FIG. 1 is an equivalent circuit diagram showing memory cells of a NAND flash memory.
As shown in FIG. 1, the memory cell contains a selection transistor, a plurality of cell transistors (cell transistors 1 to 4), and a switching transistor that are connected to each other between a bit and a source lines. Each cell transistor has a floating gate. In this specification, the memory cell shown in FIG. 1 will be called a memory cell string for convenience. Memory cell strings are arranged in a matrix on a memory cell array, as shown in FIG. 2.
In the NAND flash memory in which one cell transistor stores 1-bit data, logic values xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d of data stored in the cell transistor correspond to xe2x80x9cpositivexe2x80x9d and xe2x80x9cnegativexe2x80x9d of the threshold voltage of the cell transistor, respectively. Whether the threshold voltage of the cell transistor is xe2x80x9cpositivexe2x80x9d or xe2x80x9cnegativexe2x80x9d is determined in accordance with an electron charge state in the floating gate. When electrons are injected in the floating gate, the threshold voltage is xe2x80x9cpositivexe2x80x9d; and when electrons are discharged from the floating gate, the threshold voltage is xe2x80x9cnegativexe2x80x9d. Electrons are injected/discharged to/from the floating gate via the first gate insulating film between the floating gate and the channel region using the tunnel effect.
In writing data in the cell transistor, the switching transistor is turned xe2x80x9coffxe2x80x9d.
In reading out data from the cell transistor, the switching transistor is turned xe2x80x9conxe2x80x9d. At the same time, the selection transistor connected to a cell transistor (to be referred to as a selected cell transistor) from which data is to be read out is turned xe2x80x9conxe2x80x9d. The control gate of the selected cell transistor is set to logic xe2x80x9c0xe2x80x9d (e.g., ground potential), whereas the control gate of each unselected cell transistor is set to logic xe2x80x9c1xe2x80x9d. If the threshold voltage of the selected cell transistor is xe2x80x9cnegativexe2x80x9d, and its control gate is at logic xe2x80x9c0xe2x80x9d, the cell transistor is turned xe2x80x9conxe2x80x9d; and if the threshold of the selected cell transistor is xe2x80x9cpositivexe2x80x9d, and its control gate is at logic xe2x80x9c0xe2x80x9d, the cell transistor is turned xe2x80x9coffxe2x80x9d. In this manner, the data logic is discriminated between xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d depending on whether the selected cell transistor is xe2x80x9cONxe2x80x9d or xe2x80x9cOFFxe2x80x9d. Since the control gate of each unselected cell transistor is set to logic xe2x80x9c1xe2x80x9d, the unselected cell transistor is turned xe2x80x9conxe2x80x9d regardless of whether the threshold voltage is xe2x80x9cpositivexe2x80x9d or xe2x80x9cnegativexe2x80x9d.
In the NAND flash memory, each unselected cell transistor among series connected cell transistors is turned xe2x80x9conxe2x80x9d. Data stored in a selected cell transistor is read out depending on whether the selected cell transistor is turned xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d, i.e., a current flows or does not flow through the memory cell string.
When the selection transistor is xe2x80x9cnot selectedxe2x80x9d, the control gate of a cell transistor connected to the unselected selection transistor is set to logic xe2x80x9c0xe2x80x9d to stand by.
To store data of a plurality of bits in one cell transistor in the NAND flash EEPROM, a plurality of threshold voltages are set for the cell transistor. For example, to store 2-bit data in one cell transistor, four threshold voltages are set, as shown in Table 1.
Vth1 less than Vth2 less than Vth3 less than Vth4
Letting (D1, D2) be 2-bit memory data, as shown in Table 1, the threshold voltages of the cell transistor correspond to combinations of data (D1, D2), respectively. For example, threshold voltages Vth1, Vth2, Vth3, and Vth4 correspond to combinations (0,0), (0,1), (1,0), and (1,1) of data (D1, D2), respectively. Assuming that the threshold voltages Vth1 to Vth4 have a relation xe2x80x9cVth1 less than Vth2 less than Vth3 less than Vth4xe2x80x9d, as shown in Table 1, the threshold voltage Vth1 is set to a negative value, and the threshold voltages Vth2, Vth3, and Vth4 are set to positive values.
Data read from this cell transistor will be explained with reference to FIG. 3.
When cell transistor 2 shown in FIG. 1 is selected, a selected word line WL2 is set to a potential between the threshold voltages Vth1 and Vth2. If the threshold voltages Vth1 and Vth2 have negative and positive values, respectively, the selected word line WL2 is set to 0 V. This potential is xe2x80x9cselected word line potential 1xe2x80x9d. At this time, the potentials of unselected word lines WL1, WL3, and WL4 are set higher than the threshold voltage Vth4 so as to turn on at least one of cell transistors 1, 3, and 4 even at the highest threshold voltage Vth4 (unselected word line potential is not shown).
If the threshold voltage of cell transistor 2 is xe2x80x9cVth1xe2x80x9d, cell transistor 2 is turned on. As a result, a bit line connected to cell transistor 2 is discharged via the selection transistor, cell transistors 1 to 4, and switching transistor. This state is detected by a sense amplifier. At this time, D1=xe2x80x9c0xe2x80x9d and D2=xe2x80x9c0xe2x80x9d are determined.
If the threshold voltage of cell transistor 2 is xe2x80x9cVth2xe2x80x9d or higher, cell transistor 2 is kept off, and the bit line is kept charged.
Then, the selected word line WL2 is set to a potential between the threshold voltages Vth2 and Vth3. This potential is xe2x80x9cselected word line potential 2xe2x80x9d. If the threshold voltage of cell transistor 2 is xe2x80x9cVth2xe2x80x9d, cell transistor 2 is turned on. The bit line connected to cell transistor 2 is discharged via the selection transistor, cell transistors 1 to 4, and switching transistor. This state is detected by the sense amplifier. At this time, D1=xe2x80x9c0xe2x80x9d and D2=xe2x80x9c1xe2x80x9d are determined.
If the threshold voltage of cell transistor 2 is xe2x80x9cVth3xe2x80x9d or higher, cell transistor 2 is kept off, and the bit line is kept charged.
Then, the selected word line WL2 is set to a potential between the threshold voltages Vth3 and Vth4. This potential is xe2x80x9cselected word line potential 3xe2x80x9d. If the threshold voltage of cell transistor 2 is xe2x80x9cVth3xe2x80x9d, cell transistor 2 is turned on. The bit line connected to cell transistor 2 is discharged via the selection transistor, cell transistors 1 to 4, and switching transistor. This state is detected by the sense amplifier. At this time, D1=xe2x80x9c1xe2x80x9d and D2=xe2x80x9c0xe2x80x9d are determined.
If the threshold voltage of cell transistor 2 is xe2x80x9cVth4xe2x80x9d or higher, cell transistor 2 is kept off, and the bit line is kept charged. This state is detected by the sense amplifier. At this time, D1=xe2x80x9c1xe2x80x9d and D2=xe2x80x9c1xe2x80x9d are determined. Alternatively, the potential of the selected word line WL2 may be set to the thresh-old voltage Vth4 or higher, and the discharge state of the bit line may be detected by the sense amplifier.
Upon completion of data read, the potentials of the word lines WL1 to WL4 are set to 0 V. The potentials of the word lines of cell transistors which are connected to a selection transistor which is unselected, i.e., receives a signal SG of xe2x80x9c0xe2x80x9d are also set to 0 V.
A memory (to be referred to as a multilevel memory for convenience) in which one cell transistor stores data of a plurality of bits requires a larger number of threshold voltages than a memory (to be referred to as a binary memory for convenience) in which one cell transistor stores 1-bit data. For this reason, the highest threshold voltage in the multilevel memory becomes higher than the highest threshold voltage in the binary memory. In other words, a larger amount of electrons are injected to the floating gate in the multilevel memory than in the binary memory.
Since a larger amount of electrons are injected to the floating gate in the multilevel memory than in the binary memory, this strengthens the electric field between the floating gate and the channel, the electric field between the floating gate and the drain, and the electric field between the floating gate and the source. Consequently, the possibility of discharging electrons from the floating gate is increased. This is unpreferable in terms of memory reliability, particularly, data holding reliability.
Electrons are injected to the floating gate via the gate insulating film between the floating gate and the channel by using the tunnel effect. To realize this, a very thin gate insulating film is formed, and the reliability of this thin gate insulating film is very important. However, the potential of the word line of a cell transistor connected to a selection transistor which receives the signal SG of xe2x80x9c0xe2x80x9d is set to 0 V. Since a larger amount of electrons are injected into the floating gate in the multilevel memory than in the binary memory, the electric field applied to the thin gate insulating film strengthens. Hence, it is difficult to ensure the same reliabilty of the thin gate insulating film as that of the binary memory.
A semiconductor memory device according to an aspect of the present invention comprises: a memory cell array in which cell transistors each having a charge accumulation layer are arranged in a matrix; and a potential supply circuit configured, a least in a read operation, to supply a potential different from a ground potential to gares of the cell transistors when the memory cell array is unselected.
To achieve the main object, in a nonvolatile semiconductor memory according to the present invention, when a selection transistor is unselected, a potential different from the ground potential is supplied to the gate of a cell transistor connected to the unselected selection transistor. This can relax the electric field generated around a charge accumulation layer, compared to the prior art in which the ground potential is supplied to the gate of the cell transistor connected to the unselected selection transistor. Since the electric field generated around the charge accumulation layer is relaxed, charges are prevented from being emitted by the charge accumulation layer. A decrease in data holding reliability is suppressed.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.